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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:44:31 04/27/2010 
-- Design Name: 
-- Module Name:    sinlut - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sinlookup is
    Port ( CLOCK : in  STD_LOGIC;
           LUT_ADDRESS : in  STD_LOGIC_VECTOR (5 downto 0);
           OUTX : out  STD_LOGIC_VECTOR (15 downto 0));
end sinlookup;

architecture Behavioral of sinlookup is
component sinlut
	port (
	clka: IN std_logic;
	addra: IN std_logic_VECTOR(5 downto 0);
	douta: OUT std_logic_VECTOR(15 downto 0));
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of sinlut: component is true;

begin

U4 : sinlut
		port map (
			clka => CLOCK,
			addra => LUT_ADDRESS,
			douta => OUTX);

end Behavioral;

